The invention relates to technology for designing, verifying, and simulating an electronic design, such as the design of an integrated circuit (“IC”).
Modern electronic design is typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL (Register Transfer Level)), and then proceeds to physical design and verification.
An important step in the process of designing and constructing integrated circuits is simulation. Indeed, simulation can and should be performed during the design process to ensure that the ultimate goals are achievable and will be realized by the finished product. The exploding demand for high performance electronic products has increased interest in efficient and accurate simulation techniques for integrated circuits. For analog designs, an analog-based simulation approach such as SPICE is commonly used to implement simulation of the design. For digital circuit, equivalent digital simulation is performed.
With a growing complexity of System-On-A-Chip (SOC) designs, performing mixed-signal simulation has become a very critical aspect of design verification process. A mixed-signal design contains analog as well as digital blocks that interact with each other. The analog blocks require continuous time-domain (analog) simulators to compute their behavior while digital blocks rely on discrete time event driven (digital) simulators. A mixed-signal simulator uses both analog and digital simulation paradigms and performs the required inter-domain communication to simulate the interaction between analog and digital blocks. Such inter-domain communication is a very important component for controlling the accuracy and performance of the mixed-signal simulation. Hardware description languages, such as Verilog-AMS and VHDL-AMS, allow for effective modeling and simulation of mixed-signal designs.
In order to gain simulation/verification speed-ups, electronic designers often use complex types or models in the hardware description language to model circuit behavior. VHDL real number models are examples of complex types that may be defined to mimic analog behavior. VHDL real number models use advanced VHDL language that supports signal types that have the accuracy of real numbers and use fast discrete-domain simulation techniques for computation. This provides a good blend of accuracy and performance for simulating mixed-signal/analog functionality to cater the current mixed-signal verification needs. The VHDL language offers flexibility in terms of creating user defined signal type, clubbing multiple values on a single signal connection (commonly called user defined record types), as well as programming approaches to resolve signal interactions. This complex language features can result into a highly complex VHDL real number model that has ability to model typical analog circuit effects. In a typical mixed-signal design, such complex VHDL real number models are needed to be simulated with analog/SPICE level blocks.
Mixing of complex VHDL models/types and SPICE blocks is a very challenging problem with regard to simulation, since there is no language/standard in place today to allow for such interaction. It is noted that conventionally, neither VHDL nor VHDL-AMS allows or permits identification of SPICE blocks/instances. Moreover, the complexity of VHDL signal types complicates the problem further since designers need to worry about how such complex VHDL signals can be made to talk to SPICE blocks. Such VHDL-SPICE interaction problems have posed severe limitations in their use in a mixed-signal verification flow.
The concept of digital-analog interaction exists in AMS modeling languages such as Verilog-AMS. However, the concept of VHDL-SPICE interaction is very different. The VHDL/VHDL-AMS standard languages do not recognize SPICE as a valid construct/language. Also, VHDL is a strictly typed-language that (unlike Verilog-AMS) does not allow direct interaction of digital and analog signals. Moreover, the complexity of VHDL signals and the flexibility it offers to its modelers makes it very challenging to simulate its interaction with SPICE.
Therefore, there is a need for an improved approach for verifying and simulating mixed signal electronic circuits.